Manual de VHDL síntesis lógica para PLDs /
I tiakina i:
| Kaituhi matua: | |
|---|---|
| Kaituhi rangatōpū: | |
| Hōputu: | īPukapuka |
| Reo: | Pāniora |
| I whakaputaina: |
Bilbao :
Universidad de Deusto,
2005.
|
| Putanga: | 2a. ed. rev. y ampl. |
| Rangatū: | Ingeniería
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| Ngā marau: | |
| Urunga tuihono: | https://elibro.unach.elogim.com/es/lc/unach/titulos/34027 |
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